Advanced Micro Devices, Inc.

MTS Silicon Design Engineer(7)

Job Location:  Hyderabad
Job Description:  SkillSet: drawing, autocad, drafting, modeling, cad.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Key responsibilities:

Minimum 6+ years of SOC design and verification experience
Excellent at scripts, C++/UVM OOP languages
Experience in Verilog and System Verilog languages
Strong understanding of computer architecture and ASIC design flow
Experience with bus protocols (AXI, AHB, other)
Build C/C++/UVM model for simulation
Build test bench and monitors for DUT
Compose test plan and validation vectors to ensure functional completeness
Debug function/performance bugs of graphics, APU and server chips
Prefer 5 or more years of experience in the ASIC design and verification industry
Familiar with Linux Environment (including shell scripting and Linux GNU tools)
Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
Should be versatile in any one of the high-level verification flows such as SV, UVM, C++, etc., as well as knowledge of industry standard tools for verification
Should have excellent communication skills (both written and oral)
Strong problem-solving skills

Academic credentials:
  • MS/M Tech/BE in Computer Engineering/Electronics/Electrical Engineering
  • Demonstrated success in a senior IC team role with similar skills
Functional Area:  General / Other Software
Experience:  6 - 10 years
Qualification:  ("Graduation in any field")
Salary:  8 Lakh to 12 Lakh INR
Advanced Micro Devices, Inc.
Job Ad publication date: 18 Jan 2021